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ESD for space and high-reliability electronics

Radiation-hard ASICs need ESD protection that works in the same technologies, with flight-proven design and calibrated models.

Rad-hard ESD design

We developed the Rad-Hard ESD Cadence design kit and ESD protection IP for space ASICs in IMEC’s DARE library families. They cover the commercial UMC 180 nm CMOS and GlobalFoundries 22 nm FDSOI technologies.

ESD design of all ASIC pad-ring cell types, including ‘hot spare’, LVDS and mixed-voltage cells
ESD PDK extension with calibrated ESD models
Temperature characterization of space components following MIL standards, with FACET Ltd

ESD NMOS and diode-string layout cells in a rad-hard test chip — ESD NMOS and VDD I/O–VDD and VSS I/O–VSS diode-string layout cells for the rad-hard I/O library.

Flight heritage: now on orbit

A space ASIC for the Hisdesat mission, protected by our ESD PDK extension and calibrated models, is in orbit today.

We are a partner in ESA GSTP projects and sponsored the 2022 ESA AMICSA conference on radiation-hard ASIC design.

Two packaged radiation-hard ASICs — Packaged rad-hard space ASICs.

Schematic of a four-device ESD protection cell with floating P-well — Schematic of the ESD protection cell implemented in the UMC 180 nm DARE test chip.

Beyond the chip: demonstrators and systems

Alongside ESD, we support radiation-hard system development in cooperation with partners.

Radiation-hard systems design
Smart-systems design with improved reliability, including ESD
Synthesizable VHDL IP core development
DSP evaluation boards
Demonstration and application boards for ESA-developed rad-hard ASICs: ADC, DAC, CPU and DSP processors, interfaces and GPS receiver ASICs
Software tools and applications for radiation-hardened DSPs, and optimization of DSP kernels

Diagram of differential spacecraft surface charging in sunlight and shadow — Differential surface charging: sunlit and shadowed surfaces charge differently, creating large potential differences.

Spacecraft charging and ESD

In flight, self-shadowing and other effects can charge spacecraft surfaces differently, creating potential differences above 600 V outside and inside the vehicle. A discharge can then cause critical equipment failures in orbit.

Systematic studies of ESD in flight conditions have been limited, and common reliability design guidelines for spacecraft electronics are still needed. We have prepared Horizon 2020 space proposals on this topic with the University of Michigan and Astrium, and we take part in the ESD Association community discussion on spacecraft charging.

Planning a space ASIC or high-reliability design?

Tell us your technology and mission constraints, and we will outline ESD options.