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IC design for ESD reliability

We design the ESD protection cells and circuits for your product, and we co-design them with the functional circuit so protection does not cost performance.

What we do

ESD structures, circuit definition and layout are designed together with your functionality, then simulated against the stress mode you target: HBM, MM, CDM or IEC.

Design and qualification of ESD design library cells and IP for your silicon technology, CMOS or bipolar
Design, implementation and review of dedicated ESD protection circuits for ASIC, SoC, analog, RF and automotive applications
ESD–IC functionality co-design for digital, analog and RF blocks and for the full IC
ESD design rule development for your technology

Who this is for

IC library vendors and design houses building digital, mixed-signal, RF, high-voltage or space products.

Digital output pad ESD protection with initial and improved designs under a 2 kV HBM stress — Digital output pad under 2 kV HBM stress. With no gate coupling the protection is too slow and the output NMOS takes all the stress. With RC gate coupling it conducts the ESD current after 10 ns.

Application areas

Each application has its own ESD design window. We choose the protection approach that fits it.

Mixed-signal and tolerant I/O

Cascoded ESD NMOS devices protect a 5 V-tolerant I/O buffer in a 3.3 V CMOS process. The gate bias on each of the two gates changes the ESD performance and has to be optimized under real stress conditions.

Cascoded ESD NMOS cell in a 5 V tolerant I/O buffer with simulated I-V curves for different gate biases — SPICE-level model of cascoded NMOS devices in a 5 V tolerant I/O buffer in a 3.3 V, 0.25 µm CMOS technology.

Chart of low-noise amplifier figure of merit versus technology node with and without ESD capacitance — The parasitic capacitance of an ESD device lowers the achievable low-noise-amplifier figure of merit.

Two ESD-for-RF design methodologies: plug and play, and ESD-RF co-design — Two ESD-for-RF design methodologies.

RF I/O

The parasitic RC of ESD devices reduces gain and raises noise. With ‘plug and play’ you fit a small ESD device into the available RF window and accept limited ESD performance. With ESD–RF co-design the ESD cell becomes part of the RF circuit, so a stronger cell can be used and high RF ESD specs can be met.

High-voltage and automotive

Protecting open-drain high-voltage drivers is hard because the ESD design window is small: no stress current may enter the nDEMOS output driver. We design and model dedicated cells such as the nDEMOS-SCR, whose trigger voltage drops from about 25 V to about 5 V when gate bias is coupled in.

See the high-voltage case studies

TLP curves of nDEMOS and nDEMOS-SCR protection cells at different gate voltages — Dedicated ESD protection cells for high-voltage electronics: nDEMOS and nDEMOS-SCR, shown with TLP curves at different gate bias.

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Tell us about your ESD challenge

Send a short description of your technology, product or failure and we will tell you how we would approach it.