Real ESD design problems, solved with calibrated models, simulation and measurement. Select a figure to enlarge it.
Measured TLP data showed the protection did not trigger. SPICE simulation reproduced the behavior, and the re-designed cell with an added device worked as predicted. Measured and simulated curves correlate closely.
With no gate coupling the ESD clamp was too slow and the output NMOS took all the stress. Adding RC gate coupling made the protection conduct the whole ESD current after 10 ns.
Different substrate resistances across the fingers of an ESD NMOS made them conduct unevenly. Simulation showed that at 6 kV the busiest finger exceeded the 1.5 A pass level, while 2, 4 and 8 kV passed.
The small ESD design window means no stress current may enter the nDEMOS output driver. An nDEMOS-SCR clamp triggers at about 25 V with no gate bias and about 5 V with 2.5 V on the gate, against about 30 V for the nDEMOS alone.
In a 2 kV HBM simulation, a 1 kΩ gate resistor gave no voltage clamping, while 10 kΩ clamped well and moved the ESD current into the SCR protection.
Calibrated circuit models reproduce the measured voltage overshoot and trigger delay of a high-voltage protection cell. This is what lets designers optimize ESD operation speed at circuit level.
The complex snapback of nDEMOS devices is well represented by our circuit models. The snapback ΔV of about 10 V cannot be obtained with previous ESD models.
A SPICE-level model of cascoded ESD NMOS devices shows how the bias on each of the two gates shifts trigger voltage and has to be optimized under real stress conditions.
The parasitic capacitance of an ESD device lowers amplifier performance. Choosing between ‘plug and play’ and ESD–RF co-design depends on the RF spec and design space.
Layout and schematic of an ESD device implemented in a UMC 180 nm DARE test chip for ESA-approved rad-hard library development, in collaboration with IMEC.
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