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IC test and ESD characterization

We test and characterize ESD performance with HBM, CDM, MM, IEC and TLP methods, and help you build the TLP test capability on your own site.

What we do

Measurement closes the loop between design and simulation. We use it to find failure thresholds, calibrate models and verify fixes.

  • ESD testing: HBM, CDM, MM and IEC stress modes
  • TLP characterization of devices, cells and pads
  • TLP test system development for your test house or test site, for fast ESD performance checks and troubleshooting
  • Temperature characterization of components for space applications following the MIL family of standards, with FACET Ltd
  • Correlation of measured and simulated ESD behavior

Who this is for

IC design houses, test houses and OEMs that need ESD test data, or want to build in-house ESD test capability.

Current-voltage curves of a space-application component at −55, 25 and 125 degrees Celsius
TLP characterization at −55 °C, 25 °C and 125 °C, showing the shifts in breakdown, trigger and hold voltage.

Measurement you can design with

Test data feeds model calibration, and calibrated models then predict behavior you did not measure.

Measured HBM stress response and circuit simulations with different transit times showing voltage overshoot and trigger delay
1 kV HBM stress on an I/O pad. Calibrated circuit models reproduce the measured voltage overshoot and the trigger delay of the protection cell. A transit time of 5.5 ns matches the measurement and 0.3 ns does not.
Measured TLP curves of a power supply pad
Measured (left) and simulated (right) TLP curves of a power-supply pad ring cell, with the failure current marked.

Tell us about your ESD challenge

Send a short description of your technology, product or failure and we will tell you how we would approach it.

Contact usvesselin.vassilev@novorell.com

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