What we do
Verification applies the same ESD-aware simulation and rule checking to your full chip, cell by cell and path by path.
- ESD design review service for IP modules and for the full chip
- ESD design rule compliance and robustness checks, with automated verification tools and flow
- SOA-based verification: find IC components that operate outside their ESD safe operating area
- Chip-level prediction of CDM robustness
- Current-distribution analysis, for example to catch non-uniform activation of multi-finger ESD cells
Who this is for
IC design houses and library vendors who want an independent ESD review or an automated ESD check in their flow.
Verification inside your design flow
ESD verification connects marketing pin specifications, ESD technology IP, library cells, product IP and the full-chip integration.
Catching what review misses
In a power-supply pad ring cell, measurement showed that the protection never triggered. Simulation reproduced the failure, and the re-designed cell then behaved as predicted. The same loop applies to your design before it is taped out.
Tell us about your ESD challenge
Send a short description of your technology, product or failure and we will tell you how we would approach it.